This invention relates, in general, to integrated circuit layout, and more particularly, to automatically editing pre-existing layouts.
An integrated circuit technology such as Complementary Metal Oxide Semiconductors (CMOS) is widely used throughout the electronic industry. The prevalence of certain technologies has led to Computer Aided Design (CAD) Tools being developed which greatly decrease the cycle time of a circuit design and layout. In general, the CAD tools are built to be compatible with most generic integrated circuit processes. Circuit synthesis, simulation, worst case analysis, layout generation, and layout verification are a few of the tasks handled by the CAD tools.
One constant aspect of the semiconductor industry is that change occurs to produce faster, denser, cheaper, and more manufacturable integrated circuits than previous generations. Wafer processes that produce extremely small devices or devices with specific characteristics may have layout steps that are not compatible with a CAD tool. Layouts may have to be edited by hand to incorporate processing steps that are unique to a wafer process flow which can increase the development time of an integrated circuit.
It would be of great benefit if a method could be developed that allowed a CAD tool to layout circuits having process steps that differ from a generic wafer process flow.